1. Field of the Invention
The present invention relates to an adjusting method and an electronic device, and more particularly, to a method for adjusting a clock and an electronic device with the clock adjusting function.
2. Description of the Related Art
In design of electronic circuits, reset mechanisms are usually added in the circuits so that the electronic circuits return to the initial state if required. Especially at the beginning when electronic circuits are turned on (started), elements (such as registers) of the circuits are unstable. Thus, the circuits should be reset so that the elements of the circuits will be set as an initial state.
FIG. 1A is a circuit diagram showing a traditional electronic device. FIG. 1B is a configuration showing a time sequence of the electronic device of FIG. 1A. Referring to FIGS. 1A and 1B, the prior art electronic device 100 comprises a digital logic circuit group 110, a synchronizer 120 and a reset network 130. The electronic device 100 functions according to an input clock CLK_IN. When a reset signal RESET is inputted from outside to the electronic device 100, the reset signal RESET is first synchronized by the synchronizer 120. Then, the synchronized reset signal RESET is transmitted to the digital logic circuit group 110 through the reset network 130 so as to reset all elements in the digital logic circuit group 110.
Referring to FIG. 1B, usually all elements in the digital logic circuit group 110 should be reset during a cycle TCLK_IN of the input clock CLK_IN to make sure that the subsequent input signals are in operation. In the high-frequency electronic device 100, not only the cycle TCLK_IN of the input clock CLK_IN is extremely short, but also the number of elements of the digital logical circuit group 110 becomes large. Wherein, the number of sequential logic registers will also be increased. In order to make the cycle TRESET of the reset signal corresponding to each register accommodate the specification and be smaller than the cycle TCLK_IN, the cost will be tremendous. For example, the circuit may require a more sophisticated reset network 110. In a high-frequency IC layout, it costs substantial labor and layout areas to overcome the issue. As a result, the cost of the electronic device is increased and the schedule of putting products on the market is delayed.